Improvements in transport properties, i.e., carrier mobility, through strain have been demonstrated in the operating characteristics of field effect transistors (FETs). For complementary metal oxide semiconductor (CMOS) devices, an improvement in device characteristics through enhanced carrier mobility has significant potential for the fabrication of very high-speed devices. Strained silicon on a relaxed SiGe substrate is one system where such an improvement occurs, see, for example, D. K. Nayak, et al., “High Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si,” Appl. Phys. Lett., 62 (22), p. 2853–2855 (1993).
Experimental research on enhanced carrier mobility MOSFETs caused by strain has concentrated on a strained Si layer grown on a relaxed SiGe substrate. MOSFET's fabricated using the Si/SiGe system exhibit the following disadvantages:
(1) High source and drain junction leakage—the FET source and drain junctions, as well as the channel region, are formed in a strained Si area resulting in high junction leakage.
(2) The Si/SiGe system MOSFET process is not compatible with mainstream CMOS fabrication techniques requiring specially prepared substrates using molecular beam epitaxy.
(3) The Si/SiGe system MOSFET process is costly with a low production rate.
Local mechanical stress (LMS) is a viable alternative to strained Si by SiGe. The most common LMS approach is to use a stressed SiN contact etch stop to generate channel strain to enhance charge carrier mobility. Channel stain may also be produced by applying stress from the gate electrode.
It is known that silicides commonly used in semiconductor processing can have a high tensile stress. However, in order to have a significant influence on the channel, the silicide must be in close proximity to the surface of the channel. By “close proximity”, it is meant that the silicide must be within about 10 nm or less from the surface of the channel. In addition, the thickness of the silicide must be uniform if there is to be uniform channel strain for all CMOS devices.
Two of the main challenges for generating gate stress by silicides are to have a uniform silicide that is in close proximity to the channel. Thus, the need exists for a structure that is capable of minimizing the distance of the silicide to the channel within the gate stack with a high degree of uniformity and control. In other words, there is a need for providing a semiconductor structure that can generate a local mechanical stress for MOSFET channel mobility enhancement.